The present claimed invention relates to the field of semiconductor wafer fabrication. More specifically, the present claimed invention relates to a method for determining the magnification portion of misalignment error in a stepper used to fabricate patterned layers on a wafer.
Integrated circuits (ICs) are fabricated en masse on silicon wafers using well-known photolithography, etching, deposition, and polishing techniques. These techniques are used to define the size and shape of components and interconnects within a given layer of material built on a wafer. The IC is essentially built-up using a multitude of interconnecting layers, one formed on top of another. Because the layers interconnect, a need arises for ensuring that the patterns on adjacent layers of the wafer are accurately formed.
Accurate formation of an image on a wafer using photolithography depends on several error-causing variables. These variables include, but are not limited to, rotational alignment error, translational alignment error, reticle writing error, and magnification error, between the reticle and the wafer. Magnification error is one of the more important variables for accurately forming an image on a wafer. Precise magnification of images formed on each layer is critical for several reasons. For example, proper magnification is necessary to accurately shape and size devices for proper performance, as well as to ensure proper location of insulators and interconnecting conductors. Hence, a need arises for ensuring accurate magnification of an image from a reticle formed on a layer of a wafer.
Each one of the error-causing variables can be corrected by a different part of the stepper. If errors are not segregated and measured independently, then the error measurements are confounded, and the resulting corrections for each variable may be contradictory and self-defeating. Thus, a need arises for a method to segregate other error-causing variables from the magnification error, so as to yield a true magnification error measurement.
Referring now to prior art FIG. 1A, a top view of a conventional alignment reticle is shown. Alignment reticle 126 includes multiple overlay patterns 110a-110e, and a fine alignment target 132 located at an outer portion of the alignment reticle 100b. Each overlay pattern 110a-110e includes a first overlay box 130a and a second overlay box 130b, though only shown in overlay pattern 110a for clarity. Hence, the fine alignment target 132 is located a significant distance, 136 and 138, away from small overlay box 130a and large overlay box 130b. Large overlay box 130b is offset from small overlay box 130a by a distance 140.
The conventional alignment reticle and conventional magnification error measurement process is corrupted by using an alignment target having magnification error, rotational error, and/or translational error. The conventional reticle includes an alignment target at an outer location of the reticle image, 132 of prior art FIG. 1B and 126b of prior art FIG. 1A, that is projected through an outer portion 128b of the lens 128 of prior art FIG. 1A. Consequently, the alignment target created on the wafer suffers from magnification error, rotational error and translational error as well as reticle writing error. Furthermore, the conventional magnification error measurement process compares a full-field shot on each of two layers. However, a full-field shot includes errors other than magnification. Hence, the magnification measurement is confounded with other these other errors. Consequently, the magnification measurement may not be accurate, and thus compromise yield of the wafer and performance of the IC formed on the wafer. Hence, a need arises for a more accurate reticle and for more accurate shots on a wafer, with which magnification error can be measured.
Additionally, the conventional fine alignment target includes duplicative magnification error. Magnification error, such as lens distortion, typically increases towards the outer regions of the lens, due to factors such as lens irregularities and to properties of light. Additionally, the alignment target created on the wafer suffers from reticle writing error because it is located a significant distance, e.g. 136 and 138 of prior art FIG. 1B, away from the overlay patterns, e.g. 110a and 110e, used to measure the magnification error of the stepper. That is, reticle writing error can have an error rate, linear or exponential, that accumulates over the distance between two images on the reticle. Hence, if an overlay pattern is located far away from an alignment target, then the prior art magnification error check will be measuring the translational misalignment of the alignment target along with the magnification error of the stepper.
Furthermore, a large distance between the overlay pattern and the alignment targets only serves to amplify any processing error for the steps used in the alignment process, e.g. magnification error. For example, if the wafer is realigned in the stepper using a charge coupled device (CCD) and digital signal processing for pattern matching, both having a given tolerance, then this tolerance may be amplified at a location far from the alignment target. In one instance, a given rotational error at the alignment will increase with the distance, or radius, from the alignment target. This scenario is shown in the following figure, prior art FIG. 1B. Consequently, a need arises for creating an error-free alignment target. More specifically, a need arises for a method to measure magnification error using an alignment target that does not include reticle writing error, translational error, rotational error, or magnification error.
Referring now to prior art FIG. 1B, an example of a Preventative Maintenance (PM) wafer 150 with overlay boxes created therein is shown. Only one shot, shot 160b, is shown in this figure for clarity. Shot 150 has a small overlay box 160a and a large overlay box 160b, and a fine alignment target 162 formed therein. Alignment reticle 126 of prior art FIG. 1A is used to create the overlay boxes on wafer 150. However, in this example, rotational error occurs when the stepper did not accurately align to fine alignment target 162. This situation arises for the process that formed the second overlay box 160b on wafer 150. Even though the rotational error during alignment was a small angle 164, the large distance 166 between fine alignment target 162 and overlay box 160a magnifies the error to a substantial X error 162 and Y error 164. Part of this rotational error in the fine alignment target, as well as other errors such as magnification error in the fine alignment target, may be interpreted as a magnification error between boxes 160b and 160a. Consequently, the prior art alignment reticle and misalignment measurement process may actually overcorrect the stepper and possibly cause more error than originally existed.
Confounding the magnification error also occurs by not separating out a translational portion of the misalignment error prior to forming images on a wafer for the magnification error process. The alignment of a wafer for a magnification error measurement process intrinsically includes a translational error. Conventionally, the translational error is not accounted for in a magnification error measurement. If this error is not compensated for, it will affect the results of the magnification error measurement. Thus, by using the magnification level to compensate for the translational portion of the alignment error, alignment accuracy can possibly be degraded, due to miscorrection. Consequently, a need arises for compensating for the transitional error in the magnification error measurement.
The confounding of errors in the conventional magnification measurement process becomes important when considering budget overlay requirements. Budget overlay is a value associated with the allowable tolerance for manufacturing a given size of photolithography imprint. For example, a 0.2 micron technology would typically have a 0.08 micron budget overlay. However, as demand increases for smaller and smaller images, the budget overlay must decrease as well. For example, the current 0.12 micron technology only allows approximately a 0.055 micron budget overlay. Consequently, as budget overlay decreases, the error in the misalignment measurement becomes more significant. Thus, the aforementioned needs to improve accuracy of the magnification error measurement arise in light of more stringent budget overlay requirements.
In summary, a need arises for ensuring accurate alignment of multiple layers formed on a wafer. More specifically, a need arises for ensuring accurate magnification of an image formed on a layer of a wafer from a reticle. Also, a need arises for a method to segregate other error-causing variables from the magnification error, so as to yield a true magnification error measurement. A need also arises for a method to measure magnification error using an alignment target without reticle writing error, translational error, and magnification error. Furthermore, a need arises for compensating the stepper for the transitional error prior to the magnification error measurement. These needs to improve accuracy of the magnification error measurement arise in light of more stringent budget overlay requirements.
The present invention provides a method and an apparatus for ensuring accurate alignment of multiple layers formed on a wafer. More specifically, the present invention provides accurate magnification of an image formed on a layer of a wafer from a reticle. The present invention accomplishes accurate magnification by segregating other error-causing variables from the magnification error, so as to yield a true magnification error measurement. Additionally, the present invention provides a method for measuring magnification error using an alignment target free of magnification error, rotational error, and translational error. Furthermore, the present invention compensates for the transitional error in the stepper prior to the magnification error measurement. Thus, the present invention improves accuracy of the magnification error measurement, thereby satiating more stringent budget overlay requirements.
In particular, the present invention provides a method for determining the magnification error portion of total misalignment error in a stepper. In one embodiment, the method comprises a series of steps in a stepper, starting with the step of receiving a wafer, having a first pattern and an error-free fine alignment target, in the stepper. Then the stepper is adjusted for the translational error portion of the total misalignment, which was measured by another process. In another step, the wafer is aligned in the stepper using the error-free fine alignment target. Then a second pattern is created on the wafer overlaying said first pattern. In another step, the magnification error portion of the total misalignment error is determined by measuring the radial misalignment between the first pattern and the second pattern. By comparing the two sets of patterns, the present invention provides a method by which magnification error can be isolated and accounted for in the stepper. In one embodiment, the present invention may be thought of as creating an error-free alignment pattern within the wafer, over which alignment patterns with magnification-error will be placed. By comparing the two sets of patterns, the present invention provides a method by which magnification error can be isolated.
In another embodiment, the present invention recites a stepper that includes a processor and a computer readable memory. The memory contains program instructions and data that, when executed via the processor, implement the aforementioned method for determining magnification error in the stepper.
These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments illustrated in the various drawing figures.